CSC 561 Parallel & High Perf Computing

This course investigates the latest trends in high-performance computing (HPC) evolution and examines key issues in developing algorithms capable of exploiting these architectures. Over the past few years, advances in CPU clock rates have stagnated due to power dissipation issues. Instead of increasing performance through higher clock rates, the latest trends in the semiconductor industry have pushed processor development toward multi-core designs. These multi-core processors allow for more total computation to be done at lower power levels; however, applications must employ concurrent programming techniques to benefit from these processors. Sequential scientific computation will only see marginal benefits in performance from the next several generations of processors as on-chip cache sizes increase. In order to advance sequential scientific computations, we explore a variety of techniques for utilizing available computational resources through high level algorithm analysis and partitioning. These techniques rely on developing an underlying model for computation and data communication and matching it with the optimal architecture. Prerequisite: CSC 501 with grade of 'B' or better (CSC 302 with grade of 'B' or better for BS/MS students)